// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:12 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  pcs_raw_cr_decode.v
//
//  PCS RAW Control Register bus address decoder
//
//  Original Author: Dom Spagnuolo
//  Current Owner:   Dom Spagnuolo
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2015 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: spagnuol $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_cr_decode.v $
//    $DateTime: 2015/06/08 12:02:03 $
//    $Revision: #2 $
//
////////////////////////////////////////////////////////////////////////////// 

`include "dwc_e12mp_phy_x4_ns_cr_macros.v"
`include "dwc_e12mp_phy_x4_ns_pcs_raw_macros.v"

module dwc_e12mp_phy_x4_ns_pcs_raw_cr_decode
  #(parameter [`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RANGE] CR_TYPE    = `DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_CMN,
    parameter [`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RANGE] BCAST_TYPE = `DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_CMN,
    parameter [`DWC_E12MP_X4NS_CR_BANK_RANGE]         CR_BANK    = 3'h0) (

output reg  [`DWC_E12MP_X4NS_CR_BANK_DEPTH-1:0] cr_sel,
output reg                            cr_bank_sel,
input  wire [3:0]                     cr_chan_addr,
input  wire                           cr_clk,
input  wire                           cr_rst,
input  wire [15:0]                    cr_addr
);

// Generate high-level enable based on whether our bank is being
// accessed
// A bank is selected if the bank address matches and:
// 1. CR_TYPE matches and cr_chan_addr match (lane registers) OR
// 2. CR_TYPE != BCAST_TYPE and BCAST_TYPE matches (broadcast registers)
//
wire cr_bank_sel_int;
assign cr_bank_sel_int = (((cr_addr[`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RANGE] == CR_TYPE && cr_addr[`DWC_E12MP_X4NS_CR_LANE_RANGE] == cr_chan_addr) ||
                           (cr_addr[`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RANGE] == BCAST_TYPE && CR_TYPE != BCAST_TYPE)) &&
                          cr_addr[`DWC_E12MP_X4NS_CR_BANK_RANGE] == CR_BANK);

// Lower four bits of address are used for generating select lines
//
wire [`DWC_E12MP_X4NS_CR_REG_RANGE] reg_sel = cr_addr[`DWC_E12MP_X4NS_CR_REG_RANGE];

// Generate 1-hot select lines for registers
//
wire [`DWC_E12MP_X4NS_CR_BANK_DEPTH-1:0] cr_sel_int;
genvar inx;
generate
  for (inx = 0; inx < `DWC_E12MP_X4NS_CR_BANK_DEPTH; inx = inx + 1) begin : creg_sel_one_hot
    assign cr_sel_int[inx] = cr_bank_sel_int && (reg_sel == inx);
  end
endgenerate

// Capture bank select
//
always @(posedge cr_clk or posedge cr_rst) begin
  if (cr_rst)
    cr_bank_sel <= 1'b0;
  else 
    cr_bank_sel <= cr_bank_sel_int;
end

// Capture 1-hot select lines
//
always @(posedge cr_clk or posedge cr_rst) begin
  if (cr_rst)
    cr_sel <= {`DWC_E12MP_X4NS_CR_BANK_DEPTH{1'b0}};
  else
    cr_sel <= cr_sel_int;
end

endmodule
